Conventional time-slot interchange (TSI) switches utilize both data and connection memories to control routing of a plurality of input and output data streams. As illustrated by FIGS. 1 and 2A, a conventional TSI switch may operate under microprocessor control and each input data stream (RX) and output data stream (TX) may be configured as a serial stream of multi-bit (e.g., 8-bit) channels that are partitioned into fixed-duration frames. These multi-bit channels may be multiplexed in time and/or space between any one of a plurality of the input data streams and output data streams, as illustrated by FIG. 3. Conventional TSI switches are disclosed by U.S. Pat. Nos. 4,510,597 and 6,259,703 to Mitel Corporation. In sub-rate switching applications, 1-bit, 2-bit and 4-bit channels may be provided.
TSI switches typically enable users to perform manual microprocessor-based programming of individual connection memory entries with data memory addresses and switching mode data. Such manual operations may be time consuming and require substantial microprocessor bandwidth. The performance of conventional test and debugging operations on downstream elements in a communication path may also be complicated by the presence of a TSI switch in the path. In particular, to enable test and debugging operations to be performed on downstream elements, it may be necessary to set the TSI switch into a one-to-one RX-to-TX routing mode with constant delay. Unfortunately, this routing mode inherently results in multiple frames of delay through the TSI switch during debugging.
Thus, notwithstanding these TSI switches, there continues to be a need for switches that can be programmed more efficiently and facilitate more efficient testing and debugging operations.